Method for manufacturing semiconductor device, including multiple heat treatment

ABSTRACT

A semiconductor device manufacturing method having forming first and second insulating gate portions spaced from each other on a semiconductor substrate, selectively implanting the first conductivity type impurity ions to the first gate electrode and a surface layer of the semiconductor substrate adjacent to the first insulating gate portion, selectively implanting the second conductivity type impurity ions to the second gate electrode and the surface layer adjacent to the second insulating gate portion, after implanting the first and second conductivity types impurity ions, pre-annealing at a first substrate temperature, and after the pre-annealing, main-activating for the first and second types impurity ions at a second substrate temperature higher than the first substrate temperature for a treatment period shorter than a period of the pre-annealing.

CROSS REFERENCE TO RELATED APPLICATIONS

Notice: More than one reissue application has been filed for the reissueU.S. Pat. No. 7,026,205. The reissue applications numbers are Ser. No.12/081,248 (the present application) and Ser. No. 12/819,339 (acontinuation of Ser. No. 12/081,248).

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. P2003-100612 filed on Apr. 3,2003; the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for manufacturing asemiconductor device, and more particularly, to heat treatmentsnecessary for processes of diffusing and activating impurities.

2. Description of Related Art

Performance improvement in recent large-scale integrated circuits (LSI)has been achieved by enhancing the degree of integration; in otherwords, by miniaturization of the device configuring the LSI. However,with miniaturization of the device, a parasitic resistance and a shortchannel effect have been prone to occur. Hence, it becomes important toform shallow and low-resistant impurity diffusion regions (source/drainregions) in order to prevent the parasitic resistance and the shortchannel effect.

In order to lower the resistance of the impurity diffusion regions, itis important to fully activate impurities by use of a high-temperatureannealing treatment such as a rapid thermal annealing (RTA) treatmentutilizing a halogen lamp.

Meanwhile, shallow formation of the impurity diffusion regions isrealized by implanting impurity ions by means of low acceleration energyand by optimizing the subsequent annealing treatment. For example, in aflash lamp annealing method using a xenon (Xe) flash lamp, the xenonflash lamp emits white light for 10 msec or less, therebyinstantaneously supplying the energy necessary to activate theimpurities. Hence, the low-resistant and shallow impurity diffusionregions can be formed. Specifically, the flash lamp annealing methodenables the impurities implanted into monocrystalline silicon to beactivated without changing the distribution of the impurity ions at all.It should be noted that by use of an excimer laser capable of pulseoscillation, the low-resistant and shallow impurity diffusion regionscan be similarly formed.

However, in the RTA treatment using the halogen lamp, diffusioncoefficients of the impurities such as boron (B), phosphorus (P) andarsenic (As) in the monocrystalline silicon are large, and therefore,the impurities are diffused inside and outside the monocrystallinesilicon, thus making it difficult to form a shallow impurity diffusionlayer. When lowering the annealing temperature for the purpose ofrestricting the diffusion of the impurities, the activation ratio of theimpurities is greatly lowered. Hence, in accordance with the RTAtreatment using the halogen lamp, it is difficult to form thelow-resistant and shallow impurity diffusion regions.

Meanwhile, in the flash lamp annealing method, impurity ions implantedsimultaneously into a polycrystalline gate electrode when implanting theimpurity ions into the impurity diffusion regions are not diffusedeither, rather, they suffer from the annealing time which is extremelyshort. Therefore, the impurity ions implanted into the polycrystallinegate electrode are not diffused entirely into the polycrystalline gateelectrode, and a highly resistive region in which impurity concentrationis low is formed in a part of the polycrystalline gate electrode. Thisresistance increase of the gate electrode lowers the driving power ofthe transistor. Specifically, in accordance with the flash lampannealing method, even if the low-resistant and shallow impuritydiffusion regions can be formed, it is impossible to form ahigh-performance micro transistor.

SUMMARY OF THE INVENTION

An aspect of the present invention provides a method for manufacturing asemiconductor device having forming first and second insulating gateportions to be spaced from each other on a semiconductor substrate, thefirst insulating gate portion including a first gate insulating film anda first gate electrode doped with an impurity of a first conductivitytype, and the second insulating gate portion including a second gateinsulating film and a second gate electrode doped with an impurity of asecond conductivity type, selectively implanting impurity ions of thefirst conductivity type to the first gate electrode and a surface layerof the semiconductor substrate adjacent to the first insulating gateportion, selectively implanting impurity ions of the second conductivitytype to the second gate electrode and the surface layer adjacent to thesecond insulating gate portion, after implanting the impurity ions ofthe first and second conductivity types, performing pre-annealing at afirst substrate temperature, and after the pre-annealing, performingmain activation for the impurity ions of the first and second types at asecond substrate temperature higher than the first substrate temperaturefor a treatment period shorter than a period of the pre-annealing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional diagram illustrating an example of asemiconductor device manufactured in accordance with a method formanufacturing a semiconductor device according to an embodiment of thepresent invention;

FIGS. 2A to 2C, 3A, 3B, 4A and 4B are cross-sectional diagramsindividually illustrating principal manufacturing stages in the methodfor manufacturing a semiconductor device according to the embodiment ofthe present invention;

FIG. 5 is a graph showing a relationship between temperatures of asubstrate and elapsed times in pre-annealing;

FIG. 6 is a graph showing a relationship between temperatures of a firstsubstrate and treatment periods in the pre-annealing;

FIG. 7 is a graph showing a relationship between temperatures of thesubstrate and elapsed times during the pre-heating and main activation;

FIG. 8A is a graph showing a distribution of impurity concentrations ofa gate electrode of an nMOS transistor according to a first comparativeexample;

FIG. 8B is a graph showing a distribution of impurity concentrations ofa gate electrode of a pMOS transistor according to the first comparativeexample;

FIG. 9A is a graph showing a relationship between gate capacitances andgate voltages of the nMOS transistor according to the first comparativeexample;

FIG. 9B is a graph showing a relationship between gate capacitances andgate voltages of the pMOS transistor according to the first comparativeexample;

FIG. 10A is a graph showing a distribution of impurity concentrations ofan extension region of the nMOS transistor according to the firstcomparative example;

FIG. 10B is a graph showing a distribution of impurity concentrations ofan extension region of the pMOS transistor according to the firstcomparative example;

FIG. 11A is a graph showing a distribution of impurity concentrations ofa gate electrode of an nMOS transistor according to a second comparativeexample;

FIG. 11B is a graph showing a distribution of impurity concentrations ofa gate electrode of a pMOS transistor according to the secondcomparative example;

FIG. 12A is a graph showing a relationship between gate capacitances andgate voltages of the nMOS transistor according to the second comparativeexample;

FIG. 12B is a graph showing a relationship between gate capacitances andgate voltages of the pMOS transistor according to the second comparativeexample; and

FIG. 13 is a cross-sectional diagram illustrating a part of principalmanufacturing stages in a method for manufacturing a semiconductordevice according to a modification example of the embodiment of thepresent invention.

DETAILED DESCRIPTION OF EMBODIMENTS

Various embodiments of the present invention will be described withreference to the accompanying drawings. It is to be noted that the sameor similar reference numerals are applied to the same or similar partsand elements throughout the drawings, and the description of the same orsimilar parts and elements will be omitted or simplified.

Generally and as it is conventional in the representation ofsemiconductor devices, it will be appreciated that the various drawingsare not drawn to scale from one figure to another nor inside a givenfigure, and in particular that the layer thicknesses are arbitrarilydrawn for facilitating the reading of the drawings.

A “first conductivity type” and a “second conductivity type” areconductivity types opposite to each other. If the first conductivitytype is n type, then the second conductivity type is p type. Conversely,if the first conductivity type is p type, then the second conductivitytype is n type. The embodiment of the present invention will bedescribed in the case where the first conductivity type is n type andthe second conductivity type is p type.

(First Embodiment)

<Semiconductor Device>

First, a semiconductor device manufactured in accordance with a methodfor manufacturing a semiconductor device according to the embodiment ofthe present invention will be described. As illustrated in FIG. 1, thep-well 18 and the n-well 19 are disposed adjacent to each other on anupper portion including the surface of the semiconductor substrate 1made of monocrystalline silicon. On the outer circumferential portionsof the p-well 18 and the n-well 19 in the upper portion including thesurface of the semiconductor substrate 1, the device isolation region 2is embedded.

The insulating gate portion 21a is disposed on the surface of the p-well18. The insulating gate portion 21a includes the gate insulating film 3adisposed on the surface of the p-well 18, the gate electrode 4a disposedon the gate insulating film 3a, and the sidewall spacer 17a disposedadjacent to the side faces of the gate insulating film 3a and gateelectrode 4a on the surface of the p-well 18. The sidewall spacer 17aincludes the silicon nitride (Si₃N₄) film 7a disposed along the sidefaces of the gate insulating film 3a and gate electrode 4a and along thesurface of the p-well 18, and the silicon oxide (SiO₂) film 8a disposedon the silicon nitride film 7a. The extension region 6a is disposed onthe surface layer of the p-well 18 adjacent to the gate electrode 4a.The source/drain region 10a is disposed on the surface layer of thep-well 18 spaced from the gate electrode 4a.

The insulating gate portion 21b is disposed on the surface of the n-well19. The insulating gate portion 21b includes the gate insulating film 3bdisposed on the surface of the n-well 19, the gate electrode 4b disposedon the gate insulating film 3b, and the sidewall spacer 17b disposedadjacent to the side faces of the gate insulating film 3b and gateelectrode 4b on the surface of the n-well 19. The sidewall spacer 17bincludes the silicon nitride film 7b disposed along the side faces ofthe gate insulating film 3b and gate electrode 4b and along the surfaceof the n-well 19, and the silicon oxide film 8b disposed on the siliconnitride film 7b. The extension region 6b is disposed on the surfacelayer of the n-well 19 adjacent to the gate electrode 4b. Thesource/drain region 10b is disposed on the surface layer of the n-well19 spaced from the gate electrode 4b.

Each of the p-well 18, the extension region 6b and the source/drainregion 10b is a region where a III-group element such as boron (B)becoming a p-type impurity is doped to the semiconductor substrate 1made of monocrystalline silicon. Each of the n-well 19, the extensionregion 6a and the source/drain region 10a is a region where a V-groupelement such as phosphorus (P) and arsenic (As) becoming an n-typeimpurity is doped to the semiconductor substrate 1 made ofmonocrystalline silicon. The gate electrode 4a is made ofpolycrystalline silicon (polysilicon) doped with the n-type impurity.The gate electrode 4b is made of polycrystalline silicon doped with thep-type impurity. Each of the device isolation region 2, the gateinsulating films 3a and 3b and the sidewall spacers 17a and 17b is madeof an insulator such as silicon oxide, silicon nitride and silicon oxidenitride.

An n-type conductivity layer that electrically connects the source anddrain of the source/drain region 10a to each other, that is, ann-channel is formed immediately under the gate electrode 4a bycontrolling, for the p-well 18, a voltage applied to the gate electrode4a. A p-type conductive layer that electrically connects the source anddrain of the source/drain region 10b to each other, that is, a p-channelis formed immediately under the gate electrode 4b by controlling, forthe n-well 19, a voltage applied to the gate electrode 4b. As describedabove, the semiconductor device according to the first embodiment has aCMOS structure formed of an n-channel MOS type field-effect transistor(nMOS transistor) and a p-channel MOS type field-effect transistor (pMOStransistor).

<Method for Manufacturing a Semiconductor Device>

Next, a method for manufacturing the semiconductor device illustrated inFIG. 1 will be described with reference to FIGS. 2A to 2C, 3A, 3B, 4Aand 4B.

(A) First, p-type and n-type impurity ions are selectively implantedfrom the surface of the semiconductor substrate 1 by use of alithography method and an ion implantation method. Thereafter, a heattreatment for activating the implanted ions is performed, and thus, asillustrated in FIG. 2A, the p-well 18 and the n-well 19 are formedadjacent to each other on the upper portion including the surface of thesemiconductor substrate 1. Following this, the upper portion of thesemiconductor substrate 1 on the outer circumferential portions of thep-well 18 and n-well 19 is selectively removed by use of a lithographymethod and an anisotropic etching method such as a reactive ion etching(RIE) method, thus forming a trench. An insulator is selectivelyembedded into the trench by use of a chemical vapor deposition (CVD)method and a chemical mechanical polishing (CMP) method, thus formingthe device isolation region 2. Then, for example, the insulating film(silicon oxide film) 3 is uniformly deposited on the surface of thesemiconductor substrate 1 by use of the CVD method.

(B) Next, as illustrated in FIG. 2B, a polycrystalline conductive film(polycrystalline silicon film) doped with the n-type impurity is formedon the silicon oxide film 3. Specifically, the polycrystalline siliconfilm 4 substantially made of an intrinsic semiconductor is deposited onthe silicon oxide film 3 by use of the CVD method. The n-type impurityions are implanted entirely into the polycrystalline silicon film 4 byuse of the ion implantation method. For example, phosphorus ions areimplanted such that a concentration thereof can be 10¹⁹ cm⁻³ or more.Thereafter, a heat treatment is performed, and the n-type impurity ionsare diffused into the polycrystalline silicon film 4. For example, aheat treatment at 900° C. for approximately 10 minutes is conducted,whereby the phosphorus ions are uniformly diffused into the entirepolycrystalline silicon film 4. This process of diffusing the n-typeimpurity ions into the polycrystalline silicon film 4 can be conductedby an infrared lamp such as a halogen lamp, or an electric furnace orhot plate operated by resistance heating.

(C) Next, the silicon oxide film 3 and the polycrystalline silicon film4 are selectively removed by use of the photolithography method and theRIE method, and, as illustrated in FIG. 2C, the gate insulating films 3aand 3b and the gate electrodes 4a and 4b are formed. Thereafter, then-type impurity ions are selectively implanted into the upper portionincluding the surface of the p-well 18 by use of the lithography methodand the ion implantation method. For example, arsenic (As) ions areimplanted by acceleration energy of 1 keV in a dose of 1×10¹⁵ cm⁻². Inthis case, the gate electrode 4 serves as a mask for implanted ions, andthe first impurity region 5a is formed on the surface layer of thep-well 18, where the gate electrode 4a is not formed. Similarly, thep-type impurity ions are selectively implanted into the upper portionincluding the surface of the n-well 19. For example, boron (B) ions areimplanted by acceleration energy of 0.2 keV in a dose of 1×10¹⁵ cm⁻². Inthis case, the gate electrode 4b serves as a mask for implanted ions,and the first impurity region 5b is formed on the surface layer of then-well 19, where the gate electrode 4b is not formed.

(D) Next, light from a xenon (Xe) flash lamp is irradiated onto theentire surface of the semiconductor substrate 1 in a state where thesurface is heated up to approximately 400° C. This heat treatment isreferred to as “sub-activation” below. Irradiation time (treatmentperiod) is set at 1 ms, and surface density of the irradiation energy isset at 35 J/cm². Through sub-activation, the impurity elements implantedinto the first impurity regions 5a and 5b illustrated in FIG. 2C areactivated, and crystal defects of the first impurity regions 5a and 5bare recovered. Specifically, as illustrated in FIG. 3A, the firstimpurity regions 5a and 5b become the shallow extension regions 6a and6b adjacent to the gate electrodes 4a and 4b, respectively.

(E) Next, a silicon nitride (Si₃N₄) and a silicon oxide (SiO₂) film aresequentially deposited by use of the CVD method. The silicon nitridefilm and the silicon oxide film are removed by use of the RIE method,and at the time when the surface of the semiconductor substrate 1 andthe upper surfaces of the gate electrodes 4a and 4b emerge, the removalof the silicon nitride film and silicon oxide film is stopped. Asillustrated in FIG. 3B, the silicon nitride films 7a and 7b and thesilicon oxide films 8a and 8b are selectively left behind, adjacent tothe side faces of the gate electrodes 4a and 4b and gate insulatingfilms 3a and 3b, thus forming the sidewall spacers 17a and 17b of amultilayer structure.

(F) Next, a resist film is formed by a spin-coating method or the like.As illustrated in FIG. 4A, the resist pattern 15a, which has an openingin a region where the p-well 18 is formed, is created by use of thephotolithography method. The n-type impurity ions are selectivelyimplanted into the p-well 18 by use of the resist pattern 15a as a maskfor the implanted ions. For example, the phosphorus ions are implantedby acceleration energy of 15 keV in a dose of 3×10¹⁵ cm⁻². In this case,the n-type impurity ions are also implanted into the gate electrode 4a.Moreover, the insulating gate portion 21a becomes the mask for theimplanted ions, and the second impurity region 9a is formed on thesurface layer of the p-well 18, where the insulating gate portion 21a isnot formed. The second impurity region 9a is formed to be spaced fromthe end portion of the gate electrode 4a and deeper than the extensionregion 6a. Thereafter, the resist pattern 15a is removed.

(G) Next, a resist film is formed by the spin-coating method or thelike. As illustrated in FIG. 4B, the resist pattern 15b, which has anopening in a region where the n-well 19 is formed, is created by use ofthe photolithography method. The p-type impurity ions are selectivelyimplanted into the n-well 19 by use of the resist pattern 15b as a maskfor the implanted ions. For example, boron ions are implanted byacceleration energy of 5 keV in a dose of 3×10¹⁵ cm⁻². In this case, thep-type impurity ions are also implanted into the gate electrode 4b, andthe conductivity type thereof is inverted from the n type to the p type.In addition, the insulating gate portion 21b becomes a mask for theimplanted ions, and the second impurity region 9b is formed on thesurface layer of the n-well 19, where the insulating gate portion 21b isnot formed. The second impurity region 9b is formed to be spaced fromthe end portion of the gate electrode 4b and deeper than the extensionregion 6b. Thereafter, the resist pattern 15b is removed.

(H) Next, a heat treatment is conducted at a “first substratetemperature,” at which the n-type and p-type impurity ions implantedinto the gate electrodes 4a and 4b are diffused and the diffusion of then-type and p-type impurity ions implanted into the p-well 18 and then-well 19 is restricted. This heat treatment is referred to as“pre-annealing” below. For example, the pre-annealing is an RTAtreatment using an infrared lamp such as a halogen lamp, or an electricfurnace or hot plate operated by resistance heating. Treatmentconditions for the pre-annealing are, for example, 850° C. for the firstsubstrate temperature, and 30 seconds for the treatment period. Detailedtreatment conditions for the pre-annealing will be described later withreference to FIGS. 5 and 6.

(I) Next, after the pre-annealing, a heat treatment is conducted at a“third substrate temperature” approximately equal to or less than thatof the heat treatment illustrated in FIG. 2B for diffusing the n-typeimpurity ions into the polycrystalline silicon film 4. This heattreatment is referred to as “pre-heating” below. The pre-heating can beperformed by use of the infrared lamp or the hot plate. For example, thethird substrate temperature is approximately 400° C. Detailed treatmentconditions for the pre-heating will be described later with reference toFIG. 7.

(J) Finally, a heat treatment for activating the n-type and p-typeimpurity ions implanted into the surface layers of the p-well 18 andn-well 19 is conducted at a “second substrate temperature” higher thanthe first substrate temperature for a shorter period than that of thepre-annealing. This heat treatment is referred to as “main activation”below. For example, subsequent to the pre-heating, the light from axenon (Xe) flash lamp is irradiated entirely onto the substrate in astate where the surface of the semiconductor substrate 1 is heated up toapproximately 400° C. Irradiation time (treatment period) of the lightis set at 1 ms, and surface density of the irradiation energy on thesurface of the semiconductor substrate 1 is set at 35 J/cm².Specifically, the main activation is conducted under similar treatmentconditions to those of the sub-activation. Detailed treatment conditionsfor the sub-activation and the main activation will be described laterwith reference to FIG. 7. Through the main activation, the n-type andp-type impurity elements implanted into the surface layers of the p-well18 and n-well 19 as illustrated in FIG. 1 are activated, and the crystaldefects of the second impurity regions 9a and 9b are recovered. As aconsequence, the source/drain regions 10a and 10b deeper than theextension regions 6a and 6b are formed on the surface layers of thep-well 18 and n-well 19 spaced from the end portions of the gateelectrodes 4a and 4b, respectively. Through the stages described above,the semiconductor device which has the CMOS structure illustrated inFIG. 1 is completed.

Note that problems do not occur even if the polycrystalline silicon film4 is deposited in an atmosphere containing the n-type impurity by use ofthe CVD method in place of depositing the polycrystalline silicon film 4substantially made of the intrinsic semiconductor and implanting then-type impurity ions thereto in FIG. 2.

No problems occur even if the RTA treatment using the halogen lamp isperformed in place of the sub-activation illustrated in FIG. 3A, whichuses the xenon (Xe) flash lamp. With regard to the annealing conditionsin the RTA treatment, it is desirable that the substrate temperature be900° C. or less and that the treatment period be 10 seconds or less.Also by this RTA treatment, the impurity elements implanted into thefirst impurity regions 5a and 5b are activated without being diffuseddeeply to the semiconductor substrate 1, and the crystal defects of thefirst impurity regions 5a and 5b are recovered, thus making it possibleto form the extension regions 6a and 6b.

The n-type and p-type impurity ions implanted into the gate electrodes4a and 4b include the n-type and p-type impurity ions implanted into thegate electrodes 4a and 4b at the time of forming the first impurityregions 5a and 5b illustrated in FIG. 2C and at the time of forming thesecond impurity regions 9a and 9b illustrated in FIGS. 4A and 4B.Moreover, the n-type and p-type impurity ions implanted into the surfacelayers of the p-well 18 and n-well 19 include the n-type and p-typeimpurity ions existing in the first impurity regions 5a and 5b and thesecond impurity regions 9a and 9b.

<Pre-Annealing>

During pre-annealing, the surface of the semiconductor substrate 1 isheated up to the first substrate temperature, and the first substratetemperature is maintained for a treatment period t_(pa). In FIG. 5, theaxis of abscissas represents elapsed times from the start of heating thesemiconductor substrate 1, and the axis of ordinates representstemperatures of the surface of the semiconductor substrate 1 (substratetemperature). The substrate temperature is measured by calculating ameasurement value obtained by actually measuring the temperature of theback surface of the semiconductor substrate 1. In addition, thetreatment period t_(pa) represents the period for which the substratetemperature is maintained at the fist substrate temperature. In theexample shown in FIG. 5, the first substrate temperature is 850° C.

As shown in FIG. 6, it is desirable that the first substrate temperatureT₁ (° C.) and the treatment period t_(pa) (sec) satisfy the treatmentconditions defined by the region sandwiched by the first and secondboundary lines 31 and 32. When the first temperature T₁ is lower thanthe first boundary line 31 or the treatment period t_(pa) is shorterthan the same, the n-type and p-type impurity elements are not fullydiffused into the entire gate electrodes 4a and 4b, thus causing theresistance increase of the gate electrodes 4a and 4b. On the other hand,when the first temperature T₁ is higher than the second boundary line 32or the treatment period t_(pa) is longer than the same, the n-type andp-type impurity elements are diffused into the p-well 18 and the n-well19, and the extension regions 6a and 6b are formed to an undesirabledepth of more than 20 nm.

The first boundary line 31 is represented by the equation (1), and thesecond boundary line 32 is represented by the equation (2). Hence, thefirst substrate temperature T₁ (° C.) and the treatment time t_(pa)(sec) in the pre-annealing satisfy the treatment conditions shown in theequation (3), whereby the depths of the pn junctions of the extensionregions 6a and 6b can be maintained at 20 nm or less.t_(pa)=5×10⁻⁸exp[2.21×10⁴/(T₁+275)]  (1)t_(pa)=6×10⁻¹³exp[3.74×10⁴/(T₁+275)]  (2)5×10⁻⁸exp[2.21×10⁴/(T₁+275)]<=t_(pa)<=6×10⁻¹³exp[3.74×10⁴/(T₁+275)]  (3)

In the treatment conditions shown in FIG. 6 and the equation (3), it isfurther desirable that the substrate temperature T₁ range from 600° C.to 900° C., and preferably, 800° C. to 900° C. In addition, it isdesirable that the treatment period for the pre-annealing be in a rangefrom 5 seconds to 1 hour (3.6×10³ sec).

<Pre-Heating and Main Activation>

The pre-heating is an annealing process, in which the surface of thesemiconductor substrate 1 is heated up to the third substratetemperature, and the third substrate temperature is maintained for acertain period (pre-heating period). It is desirable that the thirdsubstrate temperature be in a range from 200° C. to 600° C., andpreferably, from 300° C. to 500° C. In the example shown in FIG. 7, thethird substrate temperature is 400° C., and the pre-heating period is 30seconds.

The main activation is conducted following pre-heating. Specifically,the main activation is conducted in a state where the temperature of thesurface of the semiconductor substrate 1 is maintained at the thirdsubstrate temperature. For the main activation, as well as the Xe flashlamp, it is possible to use light sources including a flash lamp thatenvelopes therein rare gases other than Xe, and an excimer laser and aYAG laser, both of which oscillate laser beams in a pulse shape. It isdesirable that treatment time for the main activation, that is, theperiod for irradiating light emitted from such a light source onto theentire substrate surface (flashing period of flash lamp) be 100 ms orless. Preferably, the flashing period is 10 ms or less, and morepreferably, 1 ms or less. In the example shown in FIG. 7, the flashingperiod of the flash lamp is 1 ms. Moreover, it is desirable that thesurface density of the irradiation energy of the light emitted from thelight source on the surface of the semiconductor substrate 1 be 100J/cm² or less, and preferably, 60 J/cm² or less. Note that similartreatment conditions to the above are desirable also for thesub-activation.

FIRST COMPARATIVE EXAMPLE

In a method for manufacturing a semiconductor device according to afirst comparative example of the embodiment, in FIG. 2B, the process inwhich phosphorus ions are implanted entirely into the polycrystallinesilicon film 4 by use of the ion implantation method such that theconcentration of the phosphorus ions can be 10¹⁹ cm⁻³ or more isomitted. Moreover, the subsequent heat treatment process in which thephosphorus ions are diffused into the polycrystalline silicon film 4 isomitted. Only the process in which the polycrystalline silicon film 4,made substantially of the intrinsic semiconductor, is deposited on thesilicon oxide film 3 by use of the CVD method is conducted. Furthermore,in the method for manufacturing a semiconductor device according to thefirst comparative example, the RTA treatment in the pre-annealing whichuses a halogen lamp under the conditions where the substrate temperatureis 850° C. and the treatment period is approximately 30 seconds is notperformed, but only the annealing using the xenon flash lamp isperformed in the main activation. With regard to the other manufacturingprocesses, the embodiment and the first comparative example areidentical to each other.

With regard to the impurity concentration distributions of the gateelectrodes 4a and 4b and extension regions 6a and 6b and the gatecapacitances of the MOS transistors, the semiconductor deviceillustrated in FIG. 1 and the semiconductor device manufactured inaccordance with the method for manufacturing a semiconductor deviceaccording to the first comparative example are compared with each other.Note that the embodiment and the first comparative example are alsocompared simultaneously with the related art (RTA) in which the RTAtreatment using the halogen lamp under conditions where the substratetemperature is 1015° C. and the treatment period is 10 seconds isconducted in place of the pre-annealing and the main activation.

As shown in FIGS. 8A and 8B, the impurity concentration distributions inthe gate electrodes 4a and 4b made of polysilicon were investigated byuse of secondary ion mass spectrometry (SIMS). The axis of ordinates ofFIG. 8A represents concentrations of phosphorus (P) in the gateelectrode 4a of the nMOS transistor, and the axis of ordinates of FIG.8B represents concentrations of boron (B) in the gate electrode 4b ofthe pMOS transistor. The axes of abscissas of FIGS. 8A and 8B representdepths of the gate electrodes 4a and 4b. As shown in FIGS. 8A and 8B,while the concentrations of the impurities (P and B) are substantiallyconstant in the entire gate electrodes 4a and 4b in the embodiment andthe RTA, the impurity concentrations are lowered from the midways of thegate electrodes 4a and 4b in the first comparative example.Specifically, it is understood that, while the impurities are diffuseduniformly into the entire gate electrodes 4a and 4b in the embodimentand the RTA, a difference in impurity concentration occurs in the gateelectrodes 4a and 4b, the impurity concentrations in the gate bottomsare low, and doped layers of which impurity concentrations are low areformed in the first comparative example.

As shown in FIGS. 9A and 9B, a relationship between the gate capacitance(C) and gate voltage (V) of each of the MOS transistors formed of thegate electrodes 4a and 4b, the gate insulating films 3a and 3b and thewells 18 and 19 was investigated. The axes of ordinates of FIGS. 9A and9B represent the gate capacitances, and the axes of abscissas thereofrepresent the gate voltages.

As shown in FIG. 9A, the nMOS transistors according to the embodimentand the RTA substantially coincide with each other in C-Vcharacteristics, and each nMOS transistor has a gate capacitance ofapproximately 1.15 μF/cm² when the gate voltage is 1.5V. In the firstcomparative example, the nMOS transistor has a gate capacitance ofapproximately 0.13 μF/cm² when the gate voltage is 1.5V. This gatecapacitance is lower as compared with those of the embodiment and RTA.As shown in FIG. 9B, the pMOS transistors according to the embodimentand the RTA substantially coincide with each other in C-Vcharacteristics, and each pMOS transistor has a gate capacitance ofapproximately 1.0 μF/cm² when the gate voltage is −1.5V. In the firstcomparative example, the pMOS transistor has a gate capacitance ofapproximately 0.2 μF/cm² when the gate voltage is −1.5V. This gatecapacitance is lower as compared with those of the embodiment and RTA.

As described above, it is understood that, in the first comparativeexample, the gate capacitance is lowered, and the gate insulating filmsunder the gate electrodes 4a and 4b are formed apparently thick. This isbecause, when the impurities (P and B) implanted into the gateelectrodes 4a and 4b are activated by use of the xenon flash lamp, theimpurities (P and B) are not diffused deeply into the gates, and rathersuffer from the extremely short time while the gate electrodes 4a and 4bare being subjected to the high temperature, allowing doped layers withinsufficient concentrations to form on the gate bottoms. It was alsounderstood that the insufficiently doped layers of the first comparativeexample, which were calculated based on the values of the gatecapacitances, reached 20 nm or more in thickness with respect to thegate electrodes 4a and 4b with a thickness of 150 nm.

There is a possibility that such a depletion of the gate electrodes 4aand 4b may not only lower the driving power of the transistor but alsodamage the transistor's functions. However, when the acceleration energyof the impurities implanted into the gate electrodes 4a and 4b in orderto control the depletion thereof, the impurities are deeply implantedalso into the semiconductor substrate 1, and the extension regions 6aand 6b or the source/drain regions 10a and 10b are formed deep.Furthermore, the impurity diffusion in the direction parallel to thesurface of the semiconductor substrate 1 also advances to induce theshort channel effect. In addition, the impurities pass through the gateelectrodes 4a and 4b to be diffused into the gate insulating films 3aand 3b or the surface region of the semiconductor substrate 1thereunder, thus fluctuating the threshold voltage of the transistor.

As shown in FIGS. 10A and 10B, the impurity concentration distributionsin the extension regions 6a and 6b of the nMOS transistor and the pMOStransistor were investigated by use of the SIMS. The axis of ordinatesof FIG. 10A represents the concentrations of arsenic (As) in theextension region 6a of the nMOS transistor, and the axis of ordinates ofFIG. 10B represents the concentrations of boron (B) in the extensionregion 6b of the pMOS transistor. The axes of abscissas of FIGS. 10A and10B represent the depths of the extension regions 6a and 6b. As shown inFIGS. 10A and 10B, in the embodiment and the first comparative example,the concentrations of the impurities (As and B) are radically loweredfrom the surfaces (depth: 0 nm) of the extension regions 6a and 6b, andthe impurities (As and B) are not detected in regions deeper thanapproximately 20 nm. However, as shown in FIG. 10A, in the RTA, arsenicwith a concentration of approximately 10²⁰ cm⁻³ is detected through to adepth of approximately 20 nm from the surface of the extension region6a, and arsenic continues to be detected through to a depth ofapproximately 40 nm. Moreover, as shown in FIG. 10B, in the RTA, boroncontinues to be detected through to a depth of 50 nm or more.

As described above, in the RTA treatment according to the related art,not only the impurities implanted into the gate electrodes 4a and 4bmade of polycrystalline silicon but also the impurities implanted intothe semiconductor substrate 1 made of monocrystalline silicon arediffused. Therefore, the shallow extension regions 6a and 6b of whichdepths are, for example, 20 nm or less cannot be formed.

SECOND COMPARATIVE EXAMPLE

In a method for manufacturing a semiconductor device according to asecond comparative example of the embodiment, in FIG. 2B, the process inwhich phosphorus ions are implanted entirely into the polycrystallinesilicon film 4 by use of the ion implantation method such that theconcentration of the phosphorus ions can be 10¹⁹ cm⁻³ or more isomitted. Moreover, the subsequent heat treatment process in which thephosphorus ions are diffused into the polycrystalline silicon film 4 isomitted. Only the process in which the polycrystalline silicon film 4made substantially of the intrinsic semiconductor is deposited on thesilicon oxide film 3 by use of the CVD method is conducted. With regardto the other manufacturing stages, the embodiment and the secondcomparative example are identical to each other.

With regard to the impurity concentration distributions of the gateelectrodes 4a and 4b and the gate capacitances of the MOS transistors,the semiconductor device illustrated in FIG. 1 and the semiconductordevice manufactured in accordance with the method for manufacturing asemiconductor device according to the second comparative example arecompared with each other.

As shown in FIGS. 11A and 11B, the impurity concentration distributionsin the gate electrodes 4a and 4b made of polysilicon were investigatedby use of the SIMS. The axis of ordinates of FIG. 11A representsconcentrations of phosphorus (P) in the gate electrode 4a, and the axisof ordinates of FIG. 11B represents concentrations of boron (B) in thegate electrode 4b. The axes of abscissas of FIGS. 11A and 11B representdepths of the gate electrodes 4a and 4b. As shown in FIGS. 11A and 11B,the concentrations of the impurities (P and B) are substantiallyconstant in the entire gate electrodes 4a and 4b in the embodiment.Moreover, as shown in FIG. 11B, the concentration of boron (B) issubstantially constant in the entire gate electrode 4b also in thesecond comparative example. However, as shown in FIG. 11A, theconcentration of phosphorus (P) is lowered from the midway of the gateelectrode 4a of the nMOS transistor in the second comparative example.

Specifically, in the second comparative example, it is understood that,while the boron (B) is diffused uniformly into the entire gate electrode4b in the pMOS transistor, a difference in concentration of phosphorus(P) occurs in the gate electrode 4a in the nMOS transistor, the impurityconcentration of the gate bottom is low, and doped layers withinsufficient concentrations are formed.

As shown in FIGS. 12A and 12B, a relationship between the gatecapacitance (C) and gate voltage (V) of each of the MOS transistorsformed from the gate electrodes 4a and 4b, the gate insulating films 3aand 3b and the wells 18 and 19 was investigated. The axes of ordinatesof FIGS. 12A and 12B represent the gate capacitances, and the axes ofabscissas thereof represent the gate voltages thereof.

As shown in FIG. 12B, the pMOS transistors according to the embodimentand the second comparative example substantially coincide with eachother in C-V characteristics, and each pMOS transistor has a gatecapacitance of approximately 1.0 μF/cm² when the gate voltage is −1.5V.As shown in FIG. 12A, the nMOS transistor according to the embodimenthas a gate capacitance of approximately 1.15 μF/cm² when the gatevoltage is 1.5V. However, in the second comparative example, the nMOStransistor has a gate capacitance of approximately 0.85 μF/cm² when thegate voltage is 1.5V. This gate capacitance is lower as compared withthat of the embodiment.

As described above, boron (B) is diffused into the entire gate electrode4b of the pMOS transistor in the second comparative example, andtherefore, the embodiment and the second comparative examplesubstantially coincide with each other in gate capacitance of the pMOStransistor. However, a doped layer with insufficient concentrations isformed in the gate electrode 4a of the nMOS transistor, and therefore,the gate capacitance of the nMOS transistor in the second comparativeexample is lowered as compared with that in the embodiment.Specifically, it is understood that the gate insulating film 3a underthe gate electrode 4a is formed apparently thick.

Such a difference between the nMOS transistor and the pMOS transistor inthe second comparative example originates mainly from a difference inthe ease of diffusion between the n-type impurity and the p-typeimpurity in the gate electrodes 4a and 4b. Specifically, the heattreatment conditions in the case of diffusing the impurities intopolysilicon differ between the n-type impurity and the p-type impurity.The process window of the nMOS transistor is narrower as compared withthat of the pMOS transistor. Prior to the p-type impurity of the pMOStransistor, the n-type impurity doped to the gate electrode 4a of thenMOS transistor in which the process window is narrower is doped intothe polycrystalline silicon film 4 for which the shape has not yet beenprocessed as illustrated in FIG. 2B, and then a sufficient diffusiontreatment is performed therefor. Therefore, the treatment conditions forthe pre-annealing are reduced more than those of the RTA treatmentaccording to the related art (1015° C. and 10 sec). Specifically, insuch conditions, the temperature can be lowered, and the time can beshortened. Hence, the depths of the extension regions 6a and 6b in whichthe impurity concentrations become approximately 10¹⁸ cm⁻³ arerestricted to be 20 nm or less, and simultaneously, the resistances ofthe extension regions 6a and 6b can be lowered. Thus, a stable processin which the lowering of yield is controlled can be expected.

As described above, the method for manufacturing a semiconductor deviceaccording to the embodiment of the present invention includes theplurality of heat treatment processes differing in heat treatmenttemperature and time in the event of activating the impurity ionsimplanted individually into the polycrystalline and monocrystallinesilicons. Specifically, the annealing at a low temperature for a longtime is conducted, and only the impurity ions in the polycrystallinesilicon are selectively diffused. Then, to finish, the entire implantedimpurity ions are activated in high concentration by irradiation ofhigh-brightness light at a high temperature for an extremely short time,for example, the light from a flash lamp. The diffusion of the impurityions implanted into the monocrystalline silicon can be controlled, andsimultaneously, the depletion of the gate electrodes made of thepolycrystalline silicon can be prevented. Hence, the low-resistant andshallow extension regions 6a and 6b can be formed, and simultaneously,the impurity ions in the gate electrodes 4a and 4b can be diffusedsufficiently. It becomes possible then to control the profiles of theimpurities precisely, and a high-performance MOS transistor having ashallow junction corresponding to the miniaturization can bemanufactured stably with ease.

MODIFICATION EXAMPLE OF EMBODIMENT

Although the case of implanting the n-type impurity ions to the entirepolycrystalline silicon film 4 as illustrated in FIG. 2B has beendescribed in the embodiment, the present invention is not limited tothis. It is desirable that the impurity ions of the first conductivitytype be implanting into at least a region in the polycrystalline siliconfilm 4, where the gate electrode 4a is formed.

As illustrated in FIG. 13, in the modification example of theembodiment, the polycrystalline silicon film 4 substantially made of anintrinsic semiconductor is deposited, followed by deposition of a resistfilm by the spin-coating method. The resist film is selectively removedby use of the photolithography method, thus forming the resist pattern20 which has an opening in a region where the p-well 8 is formed. Then-type impurity ions are selectively implanted into the polycrystallinesilicon film 4 on the p-well 18 by use of the resist pattern 20 as amask for the implanted ions. The ion implantation conditions in thiscase are identical to those of the embodiment. In addition, with regardto the other manufacturing processes, the embodiment and themodification example are identical to each other.

Also in accordance with the modification example of the embodiment, thedepletion of the gate electrodes 4a and 4b can be restricted, andsimultaneously, the extension regions 6a and 6b and the source/drainregions 10a and 10b can be formed shallow. Moreover, the impuritydiffusion in the direction parallel to the surface of the semiconductorsubstrate 1 can be prevented, thus making it possible to control theshort channel effect.

It is also thought that, before the shape of the polycrystalline siliconfilm is processed, not only are the n-type impurity ions selectivelyimplanted into the polycrystalline silicon film 4 on the p-well 18, butalso the p-type impurity ions are selectively implanted into thepolycrystalline silicon film 4 on the n-well 19. However, in this case,the etching rate of the RIE differs between the n-type polycrystallinesilicon film 4 and the p-type polycrystalline silicon film 4, andtherefore, the process precision of the gate electrodes 4a and 4bdeteriorates. Hence, a stable process is not obtained, thus lowering thedriving power of the transistor.

Meanwhile, in the case of the modification example, in the event ofprocessing the gate electrodes 4a and 4b illustrated in FIG. 2C, then-type polycrystalline silicon film (n-type doped region) 4 and thepolycrystalline silicon film (n-type undoped region) made of theintrinsic semiconductor will be etched simultaneously. Because theetching rate is substantially equal between the n-type doped region andthe n-type undoped region, precisely processed gate electrodes 4a and 4bcan be formed. Moreover, because the n-type impurity ions are notimplanted into the polycrystalline silicon film 4 on the n-well 19,excessive ion implantation for inverting the conductivity type of thegate electrode 4b into the p type can be avoided in the ion implantationprocess illustrated in FIG. 4B. Hence, the implantation amount of thep-type impurity can be restricted without increasing the resistance ofthe gate electrode 4b, thus making it possible to lead to thestabilization of the process.

As described above, according to the embodiment of the presentinvention, the method for manufacturing a semiconductor device havinglow-resistant and shallow impurity diffusion layers and being equippedwith good driving power can be provided.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

What is claimed is:
 1. A method for manufacturing a semiconductordevice, comprising: forming first and second insulating gate portions tobe spaced from each other on a semiconductor substrate, the firstinsulating gate portion including a first gate insulating film and afirst gate electrode doped with an impurity of a first conductivitytype, and the second insulating gate portion including a second gateinsulating film and a second gate electrode doped with an impurity of asecond conductivity type; selectively implanting impurity ions of thefirst conductivity type to the first gate electrode and a surface layerof the semiconductor substrate adjacent to the first insulating gateportion; selectively implanting impurity ions of the second conductivitytype to the second gate electrode and the surface layer adjacent to thesecond insulating gate portion; after implanting the impurity ions ofthe first and second conductivity types, performing pre-annealing at afirst substrate temperature; and after the pre-annealing, performingpre-heating of the semiconductor substrate at a third substratetemperature; and after the pre-heating, performing main activation forthe impurity ions of the first and second types at a second substratetemperature higher than the first and third substrate temperaturetemperatures for a treatment period shorter than a period of thepre-annealing and shorter than a period of the pre-heating.
 2. Themethod of claim 1, wherein the forming first and second insulating gateportions comprises: forming an insulating film on the semiconductorsubstrate; forming a polycrystalline conductive film doped with theimpurity of the first conductivity type on the insulating film; andselectively removing the insulating film and the polycrystallineconductive film to form the first and second gate insulating films andthe first and second gate electrodes.
 3. The method of claim 2, whereinthe forming first and second insulating gate portions further comprisesforming first and second sidewall spacers on the semiconductorsubstrate, the first sidewall spacer being adjacent to the first gateinsulating film and the first gate electrode, and the second sidewallspacer being adjacent to the second gate insulating film and the secondgate electrode.
 4. The method of claim 2, wherein the forming apolycrystalline conductive film comprises: depositing a polycrystallineconductive film made substantially of an intrinsic semiconductor on theinsulating film; implanting the impurity ions of the first conductivitytype at least to a region where the first gate electrode is formed inthe polycrystalline conductive film; and diffusing the impurity ions ofthe first conductivity type into the polycrystalline conductive film ata temperature equal to or higher than the third substrate temperature.5. The method of claim 3, wherein the selectively implanting impurityions of the first conductivity type comprises: selectively implantingthe impurity ions of the first conductivity type to the first gateelectrode and the surface layer adjacent to the first gate electrode;and selectively implanting the impurity ions of the first conductivitytype to the surface layer and the first gate electrode, both of whichare adjacent to the first sidewall spacer.
 6. The method of claim 5,wherein selectively implanting impurity ions of the first conductivitytype further comprises performing sub-activation for the impurity ionsof the first conductivity type at the second substrate temperature for atreatment period shorter than the period of the pre-annealing afterselectively implanting the impurity ions of the first conductivity typeto the first gate electrode and the surface layer adjacent to the firstgate electrode, and before selectively implanting the impurity ions ofthe first conductivity type to the surface layer and the first gateelectrode.
 7. The method of claim 3, wherein the selectively implantingimpurity ions of the second conductivity type comprises: selectivelyimplanting the impurity ions of the second conductivity type to thesecond gate electrode and the surface layer adjacent to the second gateelectrode; and selectively implanting the impurity ions of the secondconductivity type to the surface layer and the second gate electrode,both of which are adjacent to the second sidewall spacer.
 8. The methodof claim 7, wherein selectively implanting impurity ions of the secondconductivity type further comprises performing sub-activation for theimpurity ions of the second conductivity type at the second substratetemperature for the treatment period shorter than the period of thepre-annealing after selectively implanting the impurity ions of thesecond conductivity type to the second gate electrode and the surfacelayer adjacent to the second gate electrode, and before selectivelyimplanting the impurity ions of the second conductivity type to thesurface layer and the second gate electrode.
 9. The method of claim 1,wherein the first substrate temperature T₁ (° C.) and the treatmentperiod t_(pa) (sec) of the pre-annealing satisfy a relationshiprepresented by a following equation:5×10⁻⁸exp[2.21×10⁴/(T₁+275)]≦t_(pa)≦6×10⁻¹³exp[3.74×10⁴/(T₁+275)]. 10.The method of claim 9, wherein the first substrate temperature rangesfrom 600° C. to 900° C.
 11. The method of claim 9, wherein the treatmentperiod of the pre-annealing ranges from 5 seconds to 3.6×10³ seconds.12. The method of claim 4, wherein the pre-annealing and the diffusingthe impurity ions of the first conductivity type into thepolycrystalline conductive film are performed by use of any of aninfrared lamp, and an electric furnace and hot plate operated byresistance heating.
 13. The method of claim 1, wherein the treatmentperiod of the main activation is 100 ms or less.
 14. The method of claim13, wherein surface density of irradiation energy of light emitted froma light source for use in the main activation on a surface of thesemiconductor substrate is 100 J/cm² or less.
 15. The method of claim14, wherein the light source is a flash lamp into which a rare gas isenveloped.
 16. The method of claim 14, wherein the light source is anexcimer laser or a YAG laser, each oscillating a laser beam in a pulseshape.
 17. The method of claim 4 further comprising performingpre-heating at a third substrate temperature approximately equal to/lessthan a temperature at the diffusing the impurity ions of the firstconductivity type into the polycrystalline conductive film before themain activation, wherein the main activation is performed subsequentlyto the pre-heating.
 18. The method of claim 17 1, wherein the thirdsubstrate temperature ranges from 200° C. to 600° C.
 19. The method ofclaim 17 1, wherein the pre-heating is performed by an infrared lamporalamp or a hot plate.